1. Field of the Invention
This invention relates to integrated circuit structures constructed on semiconductor substrates. More particularly, this invention relates to a process for forming planarized isolation trenches in an integrated circuit structure on a semiconductor substrate.
2. Description of the Related Art
In the construction of integrated circuit structures, dielectric materials such as, for example, silicon oxide (SiO2) have been conventionally used to electrically separate and isolate or insulate conductive elements of the integrated circuit structure from one another. This has been carried out by growing field oxide on the surface of the semiconductor substrate, e.g, by growing silicon oxide on a silicon substrate. However, with continued shrinkage of the integrated circuit structures, more precise location of the electrical isolation regions has resulted in the formation of trenches in the semiconductor substrate which are then filled with electrical insulation material to provide the desired electrical isolation of active devices in the integrated circuit structure from one another.
Typically, when the semiconductor substrate is silicon, and a dielectric material such as silicon oxide is used as the filler material to provide the desired electrical insulation, a thin conformal layer of a different dielectric material capable of serving as an etch stop layer for the filler layer of dielectric material, such as silicon nitride, is first blanket deposited over the surface of the substrate and in the trenches as a liner material and etch stop. The remainder of each trench is then filled by blanket deposition of the filler layer of dielectric material over the liner layer on the substrate surface and in the trenches. The entire structure is then subjected to planarization such as, for example, a chemical-mechanical polish (CMP) process to remove the portions of both the liner layer and the filler layer lying on the surface of the semiconductor substrate, leaving only the liner material and the filler material in the trenches.
However, irregularities in the initial thicknesses of either the liner layer or the filler layer (or both) can occur, as shown in FIG. 1, in which a semiconductor substrate 10, hereinafter referred to as a silicon substrate by way of illustration and not of limitation, is shown having formed thereon isolation trenches 14 and 16. A liner layer 20 of dielectric material, hereinafter referred to as silicon nitride layer 20, by way of illustration and not of limitation, is first blanket deposited over the entire substrate surface, including the walls and bottom of trenches 14 and 16. A filler layer 30, hereinafter referred to as silicon oxide filler layer 30 by way of illustration and not of limitation, is then blanket deposited over silicon nitride liner 20.
In the illustrated structure of FIG. 1, it will be apparent that the right portion 30a of silicon oxide layer 30 is thicker than the left portion 30b of oxide layer 30. As a result, when the structure is subjected to a planarization process, such as, for example, a chemical-mechanical polish (CMP) process, silicon nitride 20b on the left side will become exposed, i.e., all of the overlying silicon oxide 30b will be removed, before all of the silicon oxide 30a is removed from over silicon nitride 20a on the right side of the illustrated structure in FIG. 2. While FIGS. 1 and 2 show a simplified version of the problem (for illustrative purposes only), it will be appreciated that such irregularities in thickness of either the silicon nitride layer or the silicon oxide layer can randomly occur all over the substrate.
As the prior art planarization process continues, the previously exposed silicon nitride illustrated at 20b in FIGS. 1 and 2 is then polished away while silicon oxide 30a continues to be removed from the thicker portions of the oxide/nitride layers shown on the right of FIG. 2, resulting in all of the silicon nitride and silicon oxide layers being removed at some locations on the surface of wafer 10, while silicon nitride 2a continues to be removed at other locations, as shown on the right in prior art FIG. 3. As the planarization then continues further, erosion of the top surface of the silicon oxide filler in the trench begins to occur in those location where the silicon nitride was prematurely exposed and removed, as seen at 30c in FIG. 3. By the time all of remaining silicon nitride 20a has been removed in the thicker regions, further erosion of layer 30 can result in a dishing of the top surface of the silicon oxide filler 30 in trench 14, as shown at 30d in prior art FIG. 4.
It would, therefore, be desirable to provide a planarization process which would remove the surface portions of a liner layer of dielectric material and a filler layer of a different dielectric material used to fill isolation trenches in a semiconductor substrate, while forming a planarized surface on the liner material and filler material remaining in the trenches, regardless of the initial uniformity in thickness of the liner and filler layers.
In a process for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform, the improvements which comprise:
a) removing portions of the filler layer over the liner layer on the upper surface of the substrate until portions of the underlying liner layer on the upper surface of the substrate are exposed;
b) treating the exposed portions of the liner layer to inhibit removal of the exposed liner layer portions;
c) continuing to remove the remainder of the filler layer on the liner layer over the upper surface of the substrate until all of the underlying liner layer over the upper surface of the substrate is exposed; and
d) then removing the liner layer over the upper surface of the substrate and over the filler layer in the trenches until all of the liner layer is removed from the upper surface of the substrate;
whereby removal of all of the filler layer on the liner layer over the upper surface of the substrate, while inhibiting removal of the liner layer over the upper surface of the substrate until such filler layer removal on the liner layer over the upper surface of the substrate is completed, will result in formation of a planarized surface on the upper surface of the substrate and the upper surfaces of the filler layer and the liner layer in the trenches.